The Cortex-M3 Thumb-2 instruction set - http://www.sciencezero.org Hardware registers R0-R12 General purpose registers R13 Used as stack pointer, is also called SP (can be used as a general purpose register with some restrictions) R14 Used as link register to keep the return address for fast function calls, also called LR (can be used as a general purpose register) R15 This is the program counter, also called PC Register names Rd Destination register Rn First operand register (the operation is performed on this register using the second operand, so Rd = Rn - Rm) Rm Second operand register SP Stack pointer (R13) LR Link register (R14) PC Program counter (R15) means a list of registers like {R0, R3, R7-R10} (R7-R10 is the range R7, R8, R9, R10) Immediate constants imm means a constant of n bits (a value that is fixed as assemble time and can not be changed during execution) # tells the assembler that the following is an immediate constant Parameters means always x means either x or y Optional parameters {x} means x or nothing {x|y} means either x or y or nothing Condition flags Some instructions will update the condition flags if (set condition flags) is added to the instruction name N Negative Bit 31 of the result Z Zero 1 if all bits of the result are 0 C Carry Carry from the ALU adder, otherwise from the last bit shifted out of the barrel shifter V Overflow Overflow from the ALU adder, 0x7fffffff + 0x7fffffff are two positive numbers that gives a negative result and sets the overflow flag Flag state Integer ALU / Shifter Vector Floating Point coprocessor ----------------------------------------------------------------------------------------------------- EQ Z = 1 Equal (to zero) Equal NE Z = 0 Not equal Not equal, or unordered CS / HS C = 1 Carry Set / Unsigned higher or same Greater than or equal, or unordered (two different names of the same condition) CC / LO C = 0 Carry Clear / Unsigned lower Less than (two different names of the same condition) MI N = 1 Negative Less than PL N = 0 Positive Greater than or equal, or unordered VS V = 1 Overflow Unordered (at least one NaN operand) VC V = 0 No overflow Not unordered HI C = 1 and Z = 0 Unsigned higher Greater than, or unordered LS C = 0 or Z = 1 Unsigned lower or same Less than or equal GE N = V Signed greater than or equal Greater than or equal LT N <> V Signed less than Less than, or unordered GT Z = 0 and N = V Signed greater than Greater than LE Z = 1 or N <> V Signed less than or equal Less than or equal, or unordered AL Any Always (normally omitted) Always (normally omitted) * If a two character condition code is added to the end of the instruction name, the assembler will generate the correct IT (If-Then) instructions E.g. ADDEQ r0,R0,#1 (execute the instruction if the zero flag is set) will be converted by the assembler to IT EQ ADD r0,R0,#1 may be one of the following: #imm8< #imm5 Register operation with constant shift Rm, RRX Register operation with rotate right with extend Update the condition flags after the instruction has executed If using this together with condition codes, it is in form of: ADDSEQ R0,R1,R2 Shifts LSL Logical shift left 0xFFFFFF00 LSL #4 = 0xFFFFF000 (shifts in zero at the bottom) LSR Logical shift right 0xFFFFFF00 LSR #4 = 0x0FFFFFF0 (shifts in zero at the top) ASR Arithmetic shift right 0xFFFFFF00 ASR #4 = 0xFFFFFFF0 (shifts in the original bit 31 at the top) ROR Rotate right 0x12345678 ROR #4 = 0x81234567 RRX Rotate right with extend Rotates the operand one bit to the right through the carry as a 33 bit value, Carry -> operand -> Carry Thumb-2 instruction set ---------------------- MOV{S} Rd, Move Rd = Operand2 MVN{S} Rd, Move not Rd = 0xFFFFFFFF EOR Operand2 MOV Rd, # Move wide Rd = imm16 MOVT Rd, # Move top Rd[31:16] = imm16, the constant is put in the upper 16 bits of Rd, the lower 16 bits are unaffected ADD{S} Rd, Rn, Add Rd = Rn + Operand2 ADD Rd, Rn, # Add wide Rd = Rn + Imm12 ADC{S} Rd, Rn, Add with carry Rd = Rn + Operand2 + Carry SUB{S} Rd, Rn, Subtract Rd = Rn - SBC{S} Rd, Rn, Subtract with carry Rd = Rn – Operand2 - (1 - Carry) SUB Rd, Rn, # Subtract wide Rd = Rn - imm12 RSB{S} Rd, Rn, Reverse subtract Rd = - Rn RSC{S} Rd, Rn, Reverse subtract with carry Rd = Operand2 – Rn – (1 - Carry) MUL{S} Rd, Rm, Rs Multiply Rd = Rn * Rm Returns the 32 least significant bits of the result MLA Rd, Rm, Rs, Rn Multiply and accumulate Rd = (Rn + (Rm * Rs)) Returns the 32 least significant bits of the result MLS Rd, Rm, Rs, Rn Multiply and subtract Rd = (Rn - (Rm * Rs)) Returns the 32 least significant bits of the result UMULL RdLo, RdHi, Rm, Rs Multiply unsigned long, 64 bit result UMLAL RdLo, RdHi, Rm, Rs Multiply unsigned accumulate long, 64 bit result SDIV Rd, Rn, Rm Signed division 0x80000000 / 0xFFFFFFFF = 0x80000000, Rn / 0 = 0 UDIV Rd, Rn, Rm Unsigned division Rn / 0 = 0 ASR{S} Rd, Rm, Arithmetic shift right, canonical form of MOV{S} Rd, Rm, ASR LSL{S} Rd, Rm, Logical shift left LSR{S} Rd, Rm, Logical shift right ROR{S} Rd, Rm, Rotate right RRX{S} Rd, Rm Rotate right with extent, uses Carry as a 33rd bit CLZ Rd, Rm Count leading zeros RBIT Rd, Rm Reverse bits in register, so bit 0 becomes bit 31 REV Rd, Rm Byte-Reverse Word, reverses the byte order in a 32-bit register REV16 Rd, Rm Byte-Reverse Packed Halfword, reverses the byte order in each 16-bit halfword of a 32-bit register REVSH Rd, Rm Byte-Reverse Signed Halfword, reverses the byte order in the lower 16-bit of a 32-bit register, and sign extends to 32 bit UXTB Rd, Rm{, <0|8|16|24>} Unsigned Extend Byte, extracts an 8-bit value from a register, zero extends it to 32 bit. UXTH Rd, Rm{, <0|8|16|24>} Unsigned Extend Halfword, extracts a 16-bit value from a register, zero extends it to 32 bit CMP Rn, Does the same as SUBS Rd, Rn, but the result is not written to Rd, only the condition flags are updated CMN Rn, Rn + TST Rn, Rn AND TEQ Rn, Rn EOR AND{S} Rd, Rn, Bitwise AND, Rd = Rn AND ORR{S} Rd, Rn, Bitwise OR, Rd = Rn OR EOR{S} Rd, Rn, Bitwise Exclusive-OR. Rd = Rn EOR ORN{S} Rd, Rn, Or not, Rd = Rn OR NOT BIC{S} Rd, Rn, Bit clear, Rd = Rn AND NOT BFC Rd, #, # Bit field clear BFI Rd, Rn, #, # Bit field insert SBFX Rd, Rn, #, # Signed bit field extract UBFX Rd, Rn, #, # Unsigned bit field extract
can be one of the following Example Action [Rn {, #<-imm8|+imm12>}] LDR R0, [R1, #8] R0 = [R1 + 8] [Rn {, #<+-imm8>}]! LDR R0, [R1, #8]! R1 = R1 + 8, R0 = [R1] [Rn], #<+-imm8> LDR R0, [R1], #4 R0 = [R1], R1 = R1 + 4 [Rn, Rm {, }] STR R0, [R1, R2, LSL #2] R0 = [R1 + (R2 * 4)]